1. Field of Invention
The present invention generally relates to semiconductor processing. More particularly, the present invention relates to forming a double gate structure during semiconductor device fabrication.
2. Discussion of the Related Art
With the ever-increasing number of semiconductor devices being built on a single chip, achieving vertical sidewall profiles in semiconductor devices has become an important aspect of modern semiconductor and integrated circuit technology. As composite films get thinner with shrinking transistors, volume production of memory semiconductors depends on meeting the process margins of profile and selectivity requirements simultaneously.
A high degree of etch anisotropy is desirable to produce vertical sidewalls for gate structures, thereby conforming to the required critical dimension for submicron geometries from the top to the bottom of the gate structures. A low degree of etch anisotropy will produce problems such as undesirable sloping sidewalls, causing deviations from the required critical dimension.
FIG. 1 illustrates examples of a double gate structure, including an upper gate 14 formed over a bottom gate 12, which is formed over a substrate 10. However, as illustrated in FIG. 1, conventional attempts to etch polysilicon layers to form double gate structures have encountered problems such as tapered/sloped sidewalls 20, re-entrant sidewalls 22, and notches 24 at the base of the structure.
Therefore, a method to efficiently form double gate structures with vertical sidewall profiles from the top of the control gate to the bottom of the floating gate is highly desirable in the semiconductor industry.